Defects in the manufacturing process of integrated circuits can result in circuits that do not meet the required specifications. These defects can result in hard failures or catastrophic faults, e.g., short circuits or open circuits, or can manifest themselves as subtle changes in electrical operation or parametric faults, e.g., increased current leakage or changes in circuit timing. The above-noted defects can be identified through a manufacturing test process, whereby only parts meeting all specifications are labeled as “good.”
In recent generations of CMOS process, the number of defects manifested as changes in electrical performance has been increasing. One method of finding these defects is through the use of “functional patterns” at manufacturing test to find defective parts. This method is flawed, however, because the coverage of faults in the design is usually limited. Also, functional patterns are highly sequential which result in a large, costly, pattern set occupying a lot of time on the tester.
A better method for finding these defects is an at-speed structural test, in which a test vector is set up using low-speed scan testing and the vector is exercised using the at-speed functional clock. The results are scanned out using low-speed clocks and compared to expected results. Since critical paths can be isolated in structural testing, high coverage can be achieved with an efficient pattern set using this method. However, certain faults remain difficult or impossible to test.
In recent years, normal manufacturing tolerances have become a more significant issue in digital design. With continued scaling in CMOS technologies, atomic and quantum effects now result in measurable parameter variation. As the size of the circuit features approach the atomic level, the impact of these variations increase, i.e., they become a larger percentage of the total process range. In older generations of CMOS technology, it was common to design circuits with a “buy all” strategy, i.e., the manufacturing facility would produce a model of the transistors representing a “worst case” or a “best case” process, e.g., a SPICE model. Circuit designers use the SPICE model to predict circuit performance. As long as the manufacturing line stayed within the process defined by the best case and worst case SPICE models, chips designed with these circuits, assuming they are defect free, would perform to the required specifications. However, process conformance measurement is limited, and often only indirectly measurable using process monitor structures placed at certain chip locations.
Today, the “buy all” philosophy is limited to low performance designs. For higher performance designs, if we were to apply a “buy all” philosophy, then all the variations would have to be worst-cased, and this would result in a design closure methodology that was too slow and does not meet the performance needs of the design. So even though the performance is achievable in some portion of the manufacturing window, one would not be able to close timing on such a design. Further, to obtain the highest yield possible, statistical timing techniques are used to design these chips, which allow the design team to optimize each path in the presence of manufacturing variation by predicting the sensitivity to the variation and the magnitude of the delay change of each path due to that variation.
If the design team is going to assume some process yield loss due to variation, a method is needed to identify chips that, while otherwise good, fail to meet performance specifications. In practice, this can be done with some form of delay testing. Typical methods include using specific test patterns developed by the design team, e.g., functional patterns, or a newer method where the test patterns may be derived from software that systematically looks to test a transition at each internal node or at selected internal nodes.
When chips are designed using statistical methods, a satisfactory method and device for identifying and/or “weeding out” correctly manufactured chips whose performance doesn't meet the specifications is needed. While this “weeding out” can be performed with some kind of delay based manufacturing test, these tests do not provide 100% coverage for all paths, i.e., timing requirements for some paths may not be tested at the intended performance. Thus, the chip can pass the manufacturing test even though it includes untested timing requirements that are sub-standard, e.g., due to normal process variation. In this event, the chip will be shipped to customers, and the sub-standard untested timing requirements will not be identified until the system test stage or, even worse, in the field.